Huawei Technologies has launched a new scaling law and chip architecture, known as the Tau Scaling Law, which aims to achieve a transistor density equivalent to 1.4 nanometers by 2031. He Tingbo, the chair of Huawei's Scientist Committee and president of its semiconductor division, introduced this innovative principle at the 2026 IEEE International Symposium on Circuits and Systems in Shanghai. Unlike traditional methods that rely on geometric miniaturization, the Tau Scaling Law focuses on time scaling to guide semiconductor development. Over the past six years, Huawei has leveraged this principle to design and mass-produce 381 chips. Additionally, the company introduced the LogicFolding architecture, designed to reduce resistive and capacitive loads during signal propagation, thereby increasing transistor density. The forthcoming Kirin chips, set to launch later this year, will be the first to implement this architecture. Huawei is also expanding its Ascend AI chip and Kunpeng processor development to meet domestic computing demands previously served by companies like Nvidia. The launch of the Ascend 950 series is planned for 2026, followed by the Ascend 960 in 2027 and Ascend 970 in 2028.